The invention broadly relates to a power-on reset circuitry, especially those circuits that are adapted for low power consumption and high-density integrated circuits.
In semiconductor integrated circuits (IC) with latches and memory components, initial conditions are important. Incorrect initial conditions cause severe timing problems, as well as wrong states to the IC circuits. Power-on reset circuits are designed to correct initial value problems to the IC circuits. When the power supply voltage is first applied to an IC circuit, the power-on reset circuit detects the rising power supply voltage and provides a reset signal for initializing flip-flops, latches, counters, registers and other such internal components of a semiconductor IC circuit. When the power supply voltage is on, the reset signal is at first maintained low for a sufficient time to allow stabilization of the respective components of the circuit. After a predetermined time, the reset signal is switched to a logic high to reset the components of the circuit for as long as the power supply is needed to be on. We hold the part in reset until a voltage is reached that it can operate.
To achieve effective power-on reset (POR) circuits, consideration must be given to steady-state power dissipation, chip layout, production costs and the stability of the reset signal. It is customary to design a POR circuit on the same IC area as the main circuit. Some of the IC area is devoted to the POR circuit. In addition, to save the layout area, the use of passive elements such as resistors and capacitors that occupy a relatively large area, and depletion mode transistors which require additional manufacturing steps, must be avoided. Therefore, it is desirable to have the POR occupy as little area as possible.
It is also desirable for a POR circuit to have as little current flow as possible during operation because current flow represents power consumption. The values of parasitic components vary with manufacturing process, temperature, and voltage variations. The co-existence of a plurality of p-channel and n-channel MOS transistors in many POR circuits create parasitic paths and unwanted current flows. During transition, e.g., the reset signal switched from low to high, current tends to find a way to flow from high voltage areas to lower voltage areas such as electrical ground. Therefore, parasitic components probably created by the p-type to n-type skew variations during fabrication process also needed to be minimized.
It is also desirable to have a reset signal that is stable with temperature and voltage variations. When the reset signal is not stable, the initial conditions may confuse the IC circuit at the change of condition. Usually, the reset signal varies due to temperature change and variations between p-channel and n-channel transistors during manufacturing process. The reset signal needs to change at an exact voltage level called trip voltage. If there is a skew in p-channel to n-channel in the design of the MOS triggering device such as inverters in a POR circuit, the trip voltage is shifted to an undesired value, thus delaying the reset signal and causing serious timing problems.
A large variety of power-on reset circuits have been proposed to solve the above problems, such as the one described in FIG. 1.
With reference to FIG. 1, a 3.8 volt power-on reset circuit 100 generates a reset pulse when a power supply voltage 102 ramps up from 0 volt to 5 volts. When the power supply voltage reaches 3.8 volts, the POR circuit 100 detects this voltage and generates a reset pulse.
The POR circuit 100 employs the principle of a time delay circuit coupled to a pulse detector and a series of inverter buffers to generate a reset pulse. The delay circuit has a series of diode-connected transistors to set a trip point voltage. When the trip point voltage is reached, the POR circuit 100 begins to operate. The pulse detector detects the threshold voltage and generates a pulse. The buffers either pass or invert the pulse to the output.
The operation of the POR circuit 100 can be observed at key nodes A, B and C. Referring again to FIG. 1, the gate of a first p-type zero-threshold transistor 118 of the POR circuit 100 forms node A and coupled to two inverters 136 and 138. These two inverters are coupled together in series. The output terminal of the first inverter 136 forms node B and coupled to the input of the input terminal of the second inverter 138. The output terminal of the second inverter 138 forms node C and an output PORS.
The trip point of the POR circuit 100 is set by a transistor 128. The transistor 128 has its drain coupled to the power supply voltage 102, its gate coupled to the drain and to the first terminal of a CMOS capacitor 130. The second terminal of the CMOS capacitor is coupled to the electrical ground 130. The source of the transistor 128 is coupled to the input terminal of a third inverter 132. The output terminal of the third inverter 132 is coupled to the input terminal of the fourth inverter 134.
Usually, it takes milliseconds for the power supply voltage 102 to rise from 0 volt to full value. When the power supply voltage 102 reaches the threshold voltage of 3.8 volts, the three diode-connected transistors 108, 110, and 112 start to conduct. The voltage at node A follows the rising power supply voltage 102. Before the trip point voltage set by the transistor 128 is reached, the p-type transistors 118, 120, and 122 pull down the voltage of node A to ground. The transistor 128 pulls up the output PORS because the drain is at a voltage higher than the gate and the source, which are tied together. Therefore, before the threshold voltage is reached, the voltage of node A is zero. After the trip point voltage has been reached, the voltage at node A tracks the rising voltage of the power supply voltage VCC. The transistor 128 is in the cut-off state and the voltage at the PORS terminal goes low. Thus, the voltage at the terminal C goes high. The capacitor 130 is charged up during the period the voltage at A is zero. Therefore, there are no current flows from VCC To ground when the POR circuit transitions from high to low.
An object of the invention is to provide a power-on reset circuit that has a trip point independent of the fabrication process variation and zero power consumption during operation.
Another object of the present invention is to provide a power-on reset circuit that is immune to narrow width effects within sub-micron CMOS transistor logic channel.
The above objects have been achieved by a power-on reset circuit which is implemented entirely by devices coupled together in series including a temperature-independent time delay circuit, a switching transistor having a resistor to ground for reducing leakage current and a trip point dependent on only one type of transistor, and buffers. The trip point voltage depends on only one type of transistor so that p-to-n skew due to process variations or temperature changes is not a factor. Finally, the resistor reduces threshold leakage current during voltage transitions. This permits wide transistors to be used, instead of narrow long transistors in the stack. These transistors switch more abruptly once threshold is reached, so process variations are no longer a significant factor in power consumption.